Package structure of semiconductor device with improved bonding between the substrates

ABSTRACT

A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. The outer bonding pad pattern includes first bonding pads, the inner bonding pad pattern includes second bonding pads, a density of the first bonding pads is greater than that of the second bonding pads. The first bonding pads of the outer bonding pad pattern is distributed to form a plurality of pad rings surrounding the inner bonding pad pattern, and the first bonding pads of the plurality of pad rings are aligned in a horizontal direction or a vertical direction.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of and claims thepriority benefit of U.S. patent application Ser. No. 16/781,937, filedon Feb. 4, 2020, now allowed, which claims the priority benefit ofTaiwan patent application serial no. 108148392, filed on Dec. 30, 2019.The entirety of each of the above-mentioned patent applications ishereby incorporated by reference herein and made a part of thisspecification.

BACKGROUND Technical Field

The disclosure relates to a semiconductor manufacturing technique, andmore particularly, to a package structure of a semiconductor device.

Description of Related Art

Through semiconductor manufacturing technology, an integrated circuitcan be manufactured on one substrate. The functions of the integratedcircuit have been developed towards more complex designs in response tothe overall development demands for electronic products. The number ofcomponents and interconnect structures included in an integrated circuithas thus increased significantly. There is a limit to the area of asubstrate on which components can be formed and manufactured. Due to thelarge number of components involved for enhancing the function of theintegrated circuit, the manufacturing of the integrated circuit, forexample, has been developed towards stacking in the vertical directionof the substrate to form more components and circuits.

In further manufacturing and development, the integrated circuit may bedivided into two parts which are respectively manufactured on thecorresponding substrates. A bonding layer is formed at the upper layerof the substrate. The bonding layer includes a dielectric layer, and aplurality of bonding pads are disposed in the dielectric layer. Thebonding pad is connected to a circuit formed on the substrate to bond toa circuit on another substrate. The positions of a plurality of bondingpads of the bonding layers of the two substrates are the same. In thesubsequent packaging process, the two substrates face each other, andthrough bonding of the bonding layers, the whole integrated circuit canbe formed.

In the above packaging process, if the bonding strength between the twosubstrates is insufficient, when the circuit is subsequently cut into asingle die, the bonding pads may have poor contact or even separate dueto the insufficient bonding strength, which may cause manufacturingfailure of the integrated circuit and lower the yield. Therefore, thebonding strength between the two substrates needs to be enhanced to atleast reduce damage to the circuit in the subsequent die cuttingprocess.

SUMMARY

The invention provides a layout of a bonding pad pattern on a substrate,which can improve the bonding of bonding layers and reduce thephenomenon of separation of the bonding layers between two substrates.

In an embodiment, the invention provides a package structure of asemiconductor device, including a first substrate, a second substrate,and a bonding layer. The bonding layer bonds the first substrate and thesecond substrate. The bonding layer includes an inner bonding padpattern and an outer bonding pad pattern formed in a dielectric layer,and the outer bonding pad pattern surrounds the inner bonding padpattern. The outer bonding pad pattern includes first bonding pads, theinner bonding pad pattern includes second bonding pads, a density of thefirst bonding pads of the outer bonding pad pattern is greater than adensity of the second bonding pads of the inner bonding pad pattern. Thefirst bonding pads of the outer bonding pad pattern is distributed toform a plurality of pad rings surrounding the inner bonding pad pattern,and the first bonding pads of the plurality of pad rings are aligned ina horizontal direction or a vertical direction.

In an embodiment, in the package structure of a semiconductor device,there is a first distance between two adjacent first bonding pads in theouter bonding pad pattern at the first bonding pad density, there is asecond distance between two adjacent second bonding pads in the innerbonding pad pattern at the second bonding pad density, and the firstdistance is smaller than the second distance.

In an embodiment, in the package structure of a semiconductor device,the first substrate includes a first bonding layer, the second substrateincludes a second bonding layer, and the first bonding layer and thesecond bonding layer are bonded together to form the bonding layer.

In an embodiment, in the package structure of a semiconductor device,the outer bonding pad pattern is a dummy pattern, and the inner bondingpad pattern is connected between a circuit in the first substrate and acircuit in the second substrate.

In an embodiment, in the package structure of a semiconductor device,the second bonding pads of the inner bonding pad pattern are uniformlydistributed in a square region, a rectangular region, or a circularregion.

In an embodiment, in the package structure of a semiconductor device,the outer bonding pad pattern is a right-angle quadrilateral, and eachside of the right-angle quadrilateral includes a plurality of bondingpad rows along the side.

In an embodiment, in the package structure of a semiconductor device, adistribution of the first bonding pads in each of the bonding pad rowsis the same.

In an embodiment, in the package structure of a semiconductor device,the first bonding pads of the outer bonding pad pattern are distributedto form at least two pad rings. A pad distribution of an inner ring ofthe at least two pad rings includes discontinuous regions at corners ofthe right-angle quadrilateral.

In an embodiment, in the package structure of a semiconductor device,the first bonding pads of the at least two pad rings are distributed toform at least two bonding pad rows on each side of the right-anglequadrilateral, and a length of each of the at least two bonding pad rowsis equal to a length of the corresponding side.

In an embodiment, in the package structure of a semiconductor device, ageometric shape of the first bonding pads comprises circle, square,rectangle, hexagon, or polygon, and a geometric shape of the secondbonding pads comprises circle, square, rectangle, hexagon, or polygon.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and together with the description serve to explain theprinciples of the invention.

FIG. 1A to FIG. 1C are schematic views showing a mechanism of bondingtwo substrates.

FIG. 2 is a schematic view showing a bonding pad pattern on a substrate.

FIG. 3 to FIG. 6 are schematic views showing bonding pad patterns on asubstrate according to multiple embodiments of the invention.

FIG. 7 is a schematic view showing inspection of a bonding quality ofbonding layers according to multiple embodiments of the invention.

DESCRIPTION OF THE EMBODIMENTS

The invention relates to a semiconductor packaging technique. Byplanning the bonding pad pattern on the substrate, the invention canimprove the bonding degree of a bonding layer between two substrates.The invention can reduce, for example, the phenomenon of separation ofthe bonding layer between two substrates when cutting a die.

Some embodiments will be described below to illustrate the invention,but the invention is not limited to the multiple embodiments provided.It is also possible that the multiple embodiments provided can becombined with each other.

There are various bonding techniques available for bonding betweensubstrates, e.g., a dielectric-to-dielectric bonding technique. Themechanism of dielectric-to-dielectric bonding involves performingbonding at a relatively low temperature or causing chemical reaction,between one dielectric layer and another dielectric layer to bond thedielectric materials. The bonding pads between the dielectric layers arein contact to achieve electrical connection. Afterwards, an annealingprocess at a higher temperature is performed to enhance the bondingstrength, and the bonding degree between the bonding pads will furtherachieve excellent bonding.

FIG. 1A to FIG. 1C are schematic views showing a mechanism of bondingtwo substrates. Referring to FIG. 1A, predetermined circuit structuresare completed respectively in two substrates 50 and 50A. For example,interconnect layers 52 and 52A may be formed respectively at the upperends of the substrates 50 and 50A and may also be, for example,redistribution layers (RDL) which can more uniformly redistribute theconnection endpoints. Accordingly, the endpoints to be electricallyconnected between the two interconnect layers 52 and 52A are disposed atthe same position, so that the two circuits on the two substrates 50 and50A are connected into a whole circuit. With respect to the endpoints tobe connected, a plurality of bonding pads 56 and 56A corresponding tothe endpoints to be connected are formed through bonding layers 54 and54A. The material of the bonding layers 54 and 54A includes a dielectriclayer, and the plurality of bonding pads 56 and 56A are respectivelyformed in the same pattern in the bonding layers 54 and 54A of the twosubstrates 50 and 50A. The bonding pads 56 and 56A are, for example,copper, a selected metal, or a conductive material. The bonding pads 56and 56A of the invention are not limited to specific materials. Thecircuit structures on the two substrates 50 and 50A are manufacturedseparately.

Referring to FIG. 1B, the bonding layers 54 and 54A of the two substrate50 and 50A are aligned with each other, and then the first-stagedielectric material bonding is performed, for example, by causing achemical reaction between the dielectric materials at a relatively lowtemperature to bond the dielectric materials. The corresponding bondingpads 56 and 56A which belong to the two substrates 50 and 50A will be incontact and connected. The dielectric material is generally, forexample, silicon oxide but is not limited thereto. The dielectricmaterial may also be, for example, silicon oxynitride, silicon nitride,or a similar material.

Referring to FIG. 1C, after the bonding layers 54 and 54A of the twosubstrates 50 and 50A undergo the first-stage bonding, annealing at ahigher temperature is performed to obtain a bonding layer 54B. Theeffect of annealing further enhances the bonding strength between thedielectric materials and also promotes better bonding of the bondingpads 56 and 56A.

FIG. 2 is a schematic view showing a bonding pad pattern on a substrate.Taking the bonding layer on the substrate 50 as an example, it isobserved herein that the density of the plurality of bonding pads 56 inthe bonding layer 54 is still relatively low (sparse distribution) evenafter the re-layout through the interconnect layer 52. This is becausethe number of endpoints to be actually connected between the twocircuits is not large. Here, one endpoint may be configured with aplurality of bonding pads 56, but the density is still relatively low,which may cause the bonding strength between the two substrates to beinsufficient and result in separation of the two substrates when cuttingthe die. The invention at least looks into the issue of the bonding pads56 in the bonding layer 54 and proposes a layout for the bonding pads inthe bonding layer 54.

FIG. 3 to FIG. 6 are schematic views showing bonding pad patterns on asubstrate according to multiple embodiments of the invention.

Referring to FIG. 3 , the bonding layer 54 of the substrate 50 will betaken as an example to describe the layout of the bonding pad pattern.The bonding pad pattern of the bonding layer 54A on the substrate 50A isthe same as the bonding pad pattern of the bonding layer 54 on thesubstrate 50, and they are bonded, for example, through the bondingprocess of FIG. 1A to FIG. 1C to achieve the overall connection of thetwo circuits.

In an embodiment, the bonding layer 54 includes an inner region 60 andan outer region 62. The outer region 62 surrounds the inner region 60.The geometry of the inner region 60 is, for example, a rectangle or asquare but is not limited thereto. The geometry of the inner region 60may also be a circle or other shapes. A rectangle or a square will betaken as an example in the description below.

A plurality of bonding pads 56 are disposed in the inner region 60, andthey are uniformly distributed to form an inner bonding pad pattern 57.A plurality of bonding pads 58 a and 58 b are disposed in the outerregion 62 to form an outer bonding pad pattern 58. The bonding layer 54includes a dielectric layer which surrounds the inner bonding pads 56and the outer bonding pads 58 a and 58 b. The inner bonding pad pattern57 is configured for actual bonding of circuits. The outer bonding padpattern 58 is formed of dummy bonding pads 58 a and 58 b located in theouter region 62 of the bonding layer 54 and may enhance the bondingstrength after bonding.

When cutting a die, the external force of cutting will be applied alonga scribe line, and the edge of the bonding layer 54 will be subjected tothe cutting force and is likely to be damaged. The dummy outer bondingpad pattern 58 may withstand the cutting force. Accordingly, the bondingpad density of the outer bonding pad pattern 58 should be greater thanthe bonding pad density of the inner bonding pad pattern 57.

Regarding the magnitude of the bonding pad density, in an embodiment,there is a distance d2 between two adjacent bonding pads in the outerbonding pad pattern 58 at a predetermined first bonding pad density.There is a distance d1 between two adjacent bonding pads in the innerbonding pad pattern 57 at a predetermined second bonding pad density.The high-density distance d2 is smaller than the low-density distanced1. Because the bonding pads 58 a and 58 b of the outer bonding padpattern 58 have a large bonding pad density, their mechanical strengthand bonding strength are larger, and they can withstand the externalcutting force, so that the two bonding layers 54 and 54A are less likelyto be separated.

The distribution of the plurality of bonding pads 56 of the innerbonding pad pattern 57 may be laid out according to the actualrequirements of circuit bonding. The plurality of bonding pads 58 a and58 b of the outer bonding pad pattern 58 are laid out at a greaterdensity. In an embodiment, the plurality of bonding pads 58 a and 58 bof the outer bonding pad pattern 58 are, for example, two pad rings. Thebonding pads 58 a form an inner pad ring, and the bonding pads 58 b forman outer pad ring. Based on the geometry of the inner region 60, theinner pad ring or outer pad ring formed of the bonding pads may becontinuous or may also include discontinuous local regions. For example,the inner pad ring may have discontinuous local regions at the corners.In addition, the bonding pads 58 a of the inner pad ring and the bondingpads 58 b of the outer pad ring may be laid out to be alternatelyshifted. In a vertical direction, e.g., a direction of the wide side ofthe rectangle, the bonding pads 58 a and the bonding pads 58 b areleft-right staggered. Similarly, in a horizontal direction, e.g., adirection of the long side of the rectangle, the bonding pads 58 a andthe bonding pads 58 b are up-down staggered. Accordingly, the bondingpads 58 a of the inner pad ring can block the stress passed between thebonding pads 58 b of the outer pad ring. In an embodiment, the pluralityof bonding pads 58 a and 58 b of the outer bonding pad pattern 58 do notneed to be aligned with the extending direction of the plurality ofbonding pads 56 of the inner bonding pad pattern 57. However, theinvention is not limited to the layout of the plurality of bonding pads58 a and 58 b of the outer bonding pad pattern 58 in FIG. 3 .

Referring to FIG. 4 , in an embodiment, the bonding pads 58 a of theinner pad ring and the bonding pads 58 b of the outer pad ring formed ofthe plurality of bonding pads 58 a and 58 b of the outer bonding padpattern 58 may also be aligned with each other.

In an embodiment, on the wide side and the long side of the rectangle, aplurality of rows of bonding pads 58 a and 58 b may be stacked. Forexample, two rows of bonding pads 58 a and 58 b may be stacked. However,as will be described below, the invention is not limited to this layout.The layout of the bonding pads 58 a and 58 b of FIG. 4 is only anexample provided for illustration. In an embodiment, the bonding pads 58a and 58 b at the corners may not be provided. The geometry of thebonding pads 58 a and 58 b may be, for example, a rectangle, a polygon,or a circle and is not limited to a square. In an embodiment, forexample, in FIG. 4A, the geometry of the bonding pads 58 a and 58 b is acircle. In an embodiment, for example, in FIG. 4B, the geometry of thebonding pads 58 a and 58 b is a hexagon.

In an embodiment, referring to FIG. 5 , the plurality of bonding pads ofthe outer bonding pad pattern 58 may also be laid out to be, forexample, a single pad ring, which can similarly enhance the bondingstrength at the periphery, and the invention is not limited to thelayout of two pad rings in FIG. 3 and FIG. 4 .

In an embodiment, referring to FIG. 6 , the plurality of bonding pads ofthe outer bonding pad pattern 58 may also be laid out to be, forexample, multiple pad rings such as three rings, and the invention isnot limited to the layout of two rings of FIG. 3 and FIG. 4 . Thebonding pads 58 a, 58 b, and 58 c of the three pad rings further includea pad ring of the bonding pad 58 c based on the layout of the two padrings shown in FIG. 3 or FIG. 4 .

In other words, the layout of the bonding pads of the outer bonding padpattern 58 may be changed according to the actual requirements, and agreater bonding pad density can enhance the mechanical strength andbonding strength in the peripheral region and reduce the separation ofthe two substrates during cutting.

FIG. 7 is a schematic view showing inspection of a bonding quality ofbonding layers according to multiple embodiments of the invention.Referring to FIG. 7 , herein, the bonding strength between the twobonding layers 54 and 54A of the bonding layer 54B is tested. Forexample, a knife tool 64 is used to change the applied external force,and the magnitude of the applied force for peeling the two bondinglayers 54 and 54A is observed to determine the magnitude of the bondingstrength. According to the test data, when the density of the peripheryincreases, the stress for causing peeling also increases, at an increaserate greater than the linear one-order increase rate. In other words,the arrangement of the outer bonding pad pattern 58 of the invention caneffectively prevent peeling of the two bonding layers 54 and 54A.

Lastly, it is noted that the above embodiments are only provided todescribe, rather than limit, the technical solutions of the invention.Although the invention has been described in detail with reference tothe foregoing embodiments, one of ordinary skill in the art willunderstand that he or she can still modify the technical solutionsdescribed in the foregoing embodiments, or make equivalent replacementsto some or all of the technical features. These modifications orreplacements do not cause the nature of the corresponding technicalsolutions to depart from the scope of the technical solutions of theembodiments of the invention.

What is claimed is:
 1. A package structure of a semiconductor device,comprising: a first substrate; a second substrate; and a bonding layerbonding the first substrate and the second substrate, wherein thebonding layer comprises an inner bonding pad pattern and an outerbonding pad pattern formed in a dielectric layer, and the outer bondingpad pattern surrounds the inner bonding pad pattern, wherein the outerbonding pad pattern comprises first bonding pads, the inner bonding padpattern comprises second bonding pads, a density of the first bondingpads of the outer bonding pad pattern is greater than a density of thesecond bonding pads of the inner bonding pad pattern, the first bondingpads of the outer bonding pad pattern is distributed to form a pluralityof pad rings surrounding the inner bonding pad pattern, and the firstbonding pads of the plurality of pad rings are aligned in a horizontaldirection or a vertical direction.
 2. The package structure of asemiconductor device according to claim 1, wherein there is a firstdistance between two adjacent first bonding pads in the outer bondingpad pattern at the first bonding pad density, there is a second distancebetween two adjacent second bonding pads in the inner bonding padpattern at the second bonding pad density, and the first distance issmaller than the second distance.
 3. The package structure of asemiconductor device according to claim 1, wherein the first substratecomprises a first bonding layer, the second substrate comprises a secondbonding layer, and the first bonding layer and the second bonding layerare bonded together to form the bonding layer.
 4. The package structureof a semiconductor device according to claim 1, wherein the outerbonding pad pattern is a dummy pattern, and the inner bonding padpattern is connected between a circuit in the first substrate and acircuit in the second substrate.
 5. The package structure of asemiconductor device according to claim 1, wherein the second bondingpads of the inner bonding pad pattern are uniformly distributed in asquare region, a rectangular region, or a circular region.
 6. Thepackage structure of a semiconductor device according to claim 1,wherein the outer bonding pad pattern is a right-angle quadrilateral,and each side of the right-angle quadrilateral comprises a plurality ofbonding pad rows along the side.
 7. The package structure of asemiconductor device according to claim 6, wherein a distribution of thefirst bonding pads in each of the bonding pad rows is the same.
 8. Thepackage structure of a semiconductor device according to claim 6,wherein the first bonding pads of the outer bonding pad pattern aredistributed to form at least two pad rings, wherein a pad distributionof an inner ring of the at least two pad rings comprises discontinuousregions at corners of the right-angle quadrilateral.
 9. The packagestructure of a semiconductor device according to claim 6, wherein thefirst bonding pads of the at least two pad rings are distributed to format least two bonding pad rows on each side of the right-anglequadrilateral, and a length of each of the at least two bonding pad rowsis equal to a length of the corresponding side.
 10. The packagestructure of a semiconductor device according to claim 1, wherein ageometric shape of the first bonding pads comprises circle, square,rectangle, hexagon, or polygon, and a geometric shape of the secondbonding pads comprises circle, square, rectangle, hexagon, or polygon.